1. Field of the Invention
The present invention relates to random access memories particularly to such memories fabricated with microprocessors on a single semiconductor chip.
2. Prior Art
In today's denser dynamic random access memorys (DRAMs) memory cells are arranged in a plurality of small arrays. Each of these arrays has its own set of latches associated with its sense amplifiers. These sets of latches called sense amplifier registers (SARs) are used to access, with a single access, a plurality of memory cells. In such systems, it is common, in order to conserve power, to have any array not in present use, and its associated accessing circuits, powered down to a level that will not permit either reading or writing of data. As a result of this powering down, the average access time of the memory is increased since upon being accessed a powered down array must be powered back up before data may be read out of or written into the array.
In U.S. patent application No. 510,898 entitled "Integrated Circuit I/O Using a High Performance Bus Interface" and filed on Apr. 18, 1990, it has been suggested that, by selectively pre-charging the sense amplifiers or output latches of powered down arrays, those sense amplifiers and/or latches can be used in what has been called "a poor man's cache" in which data from previous fetches, retained in the sense amplifiers or latches, can be accessed by the processors.
In U.S. patent application No. 07/887,630 filed May 22, 1992 and entitled "Advanced Parallel Array Processor" (incorporated herein by reference) a relatively large register set is used as a cache for fast temporary storage in the transfer of data between micro processors and memory arrays on the same processor chip. These registers use up significant semiconductor chip real estate. 3. Brief Description of the Invention
In accordance with the present invention, the use of such separate register sets is avoided. In their place the sense amplifier registers (SARs) of a DRAM are used for fast, temporary storage. The SARs are maintained at full operating power while the memory arrays they service may be powered down. In addition, each SAR is segmented with the segments accessible separately from one another for both reading data out and writing data into the segments without accessing the arrays. With this arrangement, the powering down of the arrays is made transparent to the microprocessor and the SARs are accessed so as to function as a cache which is accessible by the microprocessor at all times. The more arrays that are used in random access memory and the greater the number of individually accessible segments in each SAR, the deeper is the cache that is provided.
Therefore, it is an object of the present invention to provide rapid data transfer to and from random access memory to processors located on the same semiconductor chip.
Another object of the invention is to allow processors to access data in the SARs for random access memory arrays independently of accessing data stored in the arrays themselves.